1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
As semiconductor memory devices are integrated, a need for reduction of the area occupied by semiconductor elements arises. For example, in order to increase the degree of integration of a transistor, which is one of semiconductor elements, a so-called vertical transistor in which a channel is formed vertically to a substrate is known. When this structure is applied, a source electrode or a drain electrode overlaps with an active layer in which a channel is formed, so that the area occupied by the transistor can be reduced (for example, see Patent Document 1). As a result, a semiconductor memory device including such transistors can be integrated.
Semiconductor memory devices are classified into volatile semiconductor memory devices that lose stored data when power supply stops, and non-volatile semiconductor memories that hold stored data even when power supply stops.
Typical examples of volatile semiconductor memory devices are dynamic random access memories (DRAMs) and static random access memories (SRAMs). Such volatile memory devices lose stored data when supply of power is stopped, but consume relatively less power because they do not need high voltage as in non-volatile memories.
As a typical example of volatile semiconductor memory devices, a floating gate memory can be given. A floating gate memory includes a floating gate between a gate electrode and a channel formation region in a transistor and stores data by holding electric charge in the floating gate. Therefore, a flash memory has advantages in that the data holding period is extremely long (semi-permanent) and refresh operation which is necessary in a volatile memory device is not needed (for example, see Patent Document 2).
However, a gate insulating layer included in a memory element deteriorates by tunneling current generated in writing, so that the memory element stops its function after a predetermined number of writing operations. To reduce adverse effects of this problem, a method in which the number of writing operations for memory elements is equalized is employed, for example. However, a complex peripheral circuit is needed to realize this method. Moreover, employing such a method does not solve the fundamental problem of lifetime. In other words, a floating gate memory is not suitable for applications in which data is frequently rewritten.
To mend such problems of a floating gate memory, a semiconductor memory device which includes a memory cell including two transistors and one capacitor is proposed (Patent Document 3). The semiconductor memory device of the disclosed invention includes a capacitor over a gate electrode of a first transistor, and a second transistor for injecting or removing electric charge to/from the capacitor. The second transistor is formed using a material with which the off-state current of the transistor can be sufficiently small, for example, an oxide semiconductor material, which is a wide-gap semiconductor. Since the off-state current of the second transistor is sufficiently small, electric charge in the capacitor is not lost for a long period. Thus, the semiconductor memory device can hold data for a long period.
The semiconductor memory device has no problems with a function of holding data. However, there is a need for further integration of such a semiconductor memory device.